Timing Diagram Of Lhld Instruction In 8085 -

: 5 (Opcode Fetch, Memory Read, Memory Read, Memory Read, Memory Read) T-States : 2. Breakdown of Machine Cycles The timing diagram is divided into five distinct phases: Machine Cycle Description M1 Opcode Fetch 4 T-states Fetches the opcode 2Bh from memory. M2 Memory Read 3 T-states Reads the lower-byte of the 16-bit address ( M3 Memory Read 3 T-states Reads the higher-byte of the 16-bit address ( M4 Memory Read 3 T-states

: The PC places the address on the bus; ALE latches it. The processor fetches 2Bh . In T4cap T sub 4

: The processor reads the two-byte address from the memory locations immediately following the opcode. Timing Diagram Of Lhld Instruction In 8085

) : Carries the most significant bits of the memory address throughout the cycle. : Acts as the lower address bus during T1cap T sub 1 Acts as the data bus during T2cap T sub 2 T3cap T sub 3 to fetch the opcode or read memory data. Control Signals ( RD¯modified cap R cap D with bar above WR¯modified cap W cap R with bar above ) : Since LHLD is a "Load" instruction, WR¯modified cap W cap R with bar above remains high (inactive). RD¯modified cap R cap D with bar above goes low during T2cap T sub 2 T3cap T sub 3 of all five cycles to enable memory reading. Status Signals ( ) : (Memory operation). For Opcode Fetch (M1): For Memory Read (M2-M5): 4. Step-by-Step Execution

, it decodes the instruction and realizes it needs a 16-bit address. : 5 (Opcode Fetch, Memory Read, Memory Read,

To visualize the diagram, consider the following behavior of the system bus during these 16 T-states:

Uses the 16-bit address just loaded to read data into the . M5 Memory Read 3 T-states The processor fetches 2Bh

Increments the address by 1 and reads data into the . 3. Signal Behavior in the Timing Diagram